module rdy(rdyIn,lineaRdy,clock,betaRdyIn); 


  output rdyIn; 
  input lineaRdy, clock, betaRdyIn; 

  // internal register of 1 bit, used as counter modulo 2
  
  reg c; 

  // inizialization of the modulo 2 counter
  
  initial
  begin
    c = 0; 
  end

  // when getting a reset (betaRdyIn=1), do increase the counter
  
  always @ (negedge clock) 
  begin
    if(betaRdyIn==1) 
      c = ~c; 
  end

  // the output is always the comparison of the internal register with the input line
  // Pisa AE course convention: 0 stands for equal, 1 for different
  
  assign rdyIn = (lineaRdy == c ? 0 : 1 ) ; 

endmodule